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| 1 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l mx29gl256e/128e h/l datasheet www.datasheet.in
2 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l features general features ? power supply operation - 2.7 to 3.6 volt for read, erase, and program operations - v i/o voltage must tight with vcc - vi/o=vcc=2.7v~3.6v ? byte/word mode switchable - 33,554,432 x 8 / 16,777,216 x 16 (mx29gl256e h/l) - 16,777,216 x 8 / 8,388,608 x 16 (MX29GL128E h/l) ? 64kw/128kb uniform sector architecture - mx29gl256e h/l: 256 equal sectors - MX29GL128E h/l: 128 equal sectors ? 16-byte/8-word page read buffer ? 64-byte/32-word write buffer ? extra 128-word sector for security - features factory locked and identifable, and customer lockable ? advanced sector protection function (persifent and password protect) ? latch-up protected to 100ma from -1v to 1.5xvcc ? low vcc write inhibit : vcc vlko ? compatible with jedec standard - pinout and software compatible to single power supply flash ? deep power down mode performance ? high performance - fast access time: - mx29gl256e h/l: 100ns (vcc=2.7~3.6v), 90ns (vcc=3.0~3.6v) - MX29GL128E h/l: 90ns (vcc=2.7~3.6v) - page access time: 25ns - fast program time: 11us/word - fast erase time: 0.6s/sector ? low power consumption - low active read current: 30ma (typical) at 5mhz - low standby current: 30ua (typical) ? typical 100,000 erase/program cycle ? 10 years data retention software features ? program/erase suspend & program/erase resume - suspends sector erase operation to read data from or program data to another sector which is not being erased - suspends sector program operation to read data from another sector which is not being program ? status reply - data# polling & toggle bits provide detection of program and erase operation completion ? support common flash interface (cfi) hardware features ? ready/busy# (ry/by#) output - provides a hardware method of detecting program and erase operation completion ? hardware reset (reset#) input - provides a hardware method to reset the internal state machine to read mode ? wp#/acc input pin - hardware write protect pin/provides accelerated program capability package ? 56-pin tsop ? 64-ball fbga (10mm x 13mm) ? 64-ball lfbga (11mm x 13mm) ? 70-pin ssop ? all pb-free devices are rohs compliant single voltage 3v only flash memory preliminary www.datasheet.in 3 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l pin configuration 56 tsop 64 fbga/64 lfbga a b c d e f g h nc 8 7 6 5 4 3 2 1 a22 a23* vio nc nc nc a13 a12 a14 a15 a16 byte# q15/ a-1 a9 a8 a10 a11 q7 q14 q13 q6 we# a21 a19 res- et# q5 q12 vcc q4 wp#/ a cc a18 a20 q2 q10 q11 r y/ by# a7 a17 a6 a5 q0 q8 q9 q1 q3 a3 a4 a2 a1 a0 ce# oe# gnd gnd gnd nc nc nc nc nc vio nc nc a23* a22 a15 a14 a13 a12 a11 a10 a9 a8 a19 a20 we# reset# a21 wp#/acc ry/by# a18 a17 a7 a6 a5 a4 a3 a2 a1 nc nc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 nc nc a16 byte# gnd q15/a-1 q7 q14 q6 q13 q5 q12 q4 v cc q11 q3 q10 q2 q9 q1 q8 q0 oe# gnd ce# a0 nc v i/o 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 note: a23 is nc for MX29GL128E h/l note: a23 is nc for MX29GL128E h/l www.datasheet.in 4 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l 70 ssop pin description symbol pin name a0~a23 address input (a0~a23 for 256mb, a0~a22 for 128mb) q0~q14 data inputs/outputs q15/a-1 q15(word mode)/lsb addr(byte mode) ce# chip enable input we# write enable input oe# output enable input reset# hardware reset pin, active low wp#/acc* hardware write protect/programming acceleration input ry/by# read/busy output byte# selects 8 bits or 16 bits mode vcc +3.0v single power supply gnd device ground nc pin not connected internally vi/o power supply for input/output logic symbol 16 or 8 q0-q15 (a-1) r y/by# a0-a23 ce# oe# we# reset# wp#/a cc byte# vi/o 24 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 a20 a21 a18 a17 oe# a6 a5 a4 a3 a2 a1 a0 byte# gnd nc nc nc nc nc nc gnd nc ce# gnd gnd a7 q0 q8 q1 q9 q2 q10 q3 q11 nc a19 a8 a15 a10 a11 a12 a13 a14 a9 a16 we# nc a22 a23* gnd nc nc wp#/acc nc nc nc gnd reset# gnd gnd q15/a-1 q7 q14 q6 q13 q5 q12 q4 vcc vcc notes: 1. wp#/acc has internal pull up. 2. vi/o voltage must tight with vcc. vi/o = vcc =2.7v~3.6v. note: a23 is nc for MX29GL128E h/l www.datasheet.in 5 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l block diagram control input logic program/erase high voltage write state machine (wsm) state register flash array x-decoder address latch and buffer y-pass gate y-decoder array source hv command data decoder command data latch i/o buffer pgm data hv program data latch sense amplifier q0-q15/a-1 a0-am am: msb address ce# oe# we# reset# byte# wp#/acc www.datasheet.in 6 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l block diagram description the block diagram on page 4 illustrates a simplifed architecture of this device. each block in the block diagram represents one or more circuit modules in the real chip used to access, erase, program, and read the memory array. the "control input logic" block receives input pins ce#, oe#, we#, reset#, byte#, and wp#/acc. it creates internal timing control signals according to the input pins and outputs to the "address latch and buffer" to latch the external address pins a0-am(a23). the internal addresses are output from this block to the main array and decoders composed of "x-decoder", "y-decoder", "y-pass gate", and "flash ar - ray". the x-decoder decodes the word-lines of the fash array, while the y-decoder decodes the bit-lines of the fash array. the bit lines are electrically connected to the "sense amplifier" and "pgm data hv" se - lectively through the y-pass gates. sense amplifiers are used to read out the contents of the fash memo - ry, while the "pgm data hv" block is used to selectively deliver high power to bit-lines during programming. the "i/o buffer" controls the input and output on the q0-q15/a-1 pads. during read operation, the i/o buffer receives data from sense amplifiers and drives the output pads accordingly. in the last cycle of program command, the i/o buffer transmits the data on q0-q15/a-1 to "program data latch", which controls the high power drivers in "pgm data hv" to selectively program the bits in a word or byte according to the user in - put pattern. the "program/erase high voltage" block comprises the circuits to generate and deliver the necessary high voltage to the x-decoder, flash array, and "pgm data hv" blocks. the logic control module com - prises of the "write state machine, wsm", "state register", "command data decoder", and "command data latch". when the user issues a command by toggling we#, the command on q0-a15/a-1 is latched in the command data latch and is decoded by the command data decoder. the state register receives the command and records the current state of the device. the wsm implements the in - ternal algorithms for program or erase according to the current command state by controlling each block in the block diagram. array architecture the main fash memory array can be organized as byte mode (x8) or word mode (x16). the details of the ad - dress ranges and the corresponding sector addresses are shown in table 1. www.datasheet.in 7 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l table 1-1. mx29gl256eh/l sector architecture block structure sector size sector sector address a23-a16 (x16) address range kbytes kwords 128 64 sa0 00000000 000000h-00ffffh 128 64 sa1 00000001 010000h-01ffffh 128 64 sa2 00000010 020000h-02ffffh 128 64 sa3 00000011 030000h-03ffffh 128 64 sa4 00000100 040000h-04ffffh 128 64 sa5 00000101 050000h-05ffffh 128 64 sa6 00000110 060000h-06ffffh 128 64 sa7 00000111 070000h-07ffffh 128 64 sa8 00001000 080000h-08ffffh 128 64 sa9 00001001 090000h-09ffffh 128 64 sa10 00001010 0a0000h-0affffh 128 64 sa11 00001011 0b0000h-0bffffh 128 64 sa12 00001100 0c0000h-0cffffh 128 64 sa13 00001101 0d0000h-0dffffh 128 64 sa14 00001110 0e0000h-0effffh 128 64 sa15 00001111 0f0000h-0fffffh 128 64 sa16 00010000 100000h-10ffffh 128 64 sa17 00010001 110000h-11ffffh 128 64 sa18 00010010 120000h-12ffffh 128 64 sa19 00010011 130000h-13ffffh 128 64 sa20 00010100 140000h-14ffffh 128 64 sa21 00010101 150000h-15ffffh 128 64 sa22 00010110 160000h-16ffffh 128 64 sa23 00010111 170000h-17ffffh 128 64 sa24 00011000 180000h-18ffffh 128 64 sa25 00011001 190000h-19ffffh 128 64 sa26 00011010 1a0000h-1affffh 128 64 sa27 00011011 1b0000h-1bffffh 128 64 sa28 00011100 1c0000h-1cffffh 128 64 sa29 00011101 1d0000h-1dffffh 128 64 sa30 00011110 1e0000h-1effffh 128 64 sa31 00011111 1f0000h-1fffffh 128 64 sa32 00100000 200000h-20ffffh 128 64 sa33 00100001 210000h-21ffffh 128 64 sa34 00100010 220000h-22ffffh 128 64 sa35 00100011 230000h-23ffffh 128 64 sa36 00100100 240000h-24ffffh 128 64 sa37 00100101 250000h-25ffffh www.datasheet.in 8 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l sector size sector sector address a23-a16 (x16) address range kbytes kwords 128 64 sa38 00100110 260000h-26ffffh 128 64 sa39 00100111 270000h-27ffffh 128 64 sa40 00101000 280000h-28ffffh 128 64 sa41 00101001 290000h-29ffffh 128 64 sa42 00101010 2a0000h-2affffh 128 64 sa43 00101011 2b0000h-2bffffh 128 64 sa44 00101100 2c0000h-2cffffh 128 64 sa45 00101101 2d0000h-2dffffh 128 64 sa46 00101110 2e0000h-2effffh 128 64 sa47 00101111 2f0000h-2fffffh 128 64 sa48 00110000 300000h-30ffffh 128 64 sa49 00110001 310000h-31ffffh 128 64 sa50 00110010 320000h-32ffffh 128 64 sa51 00110011 330000h-33ffffh 128 64 sa52 00110100 340000h-34ffffh 128 64 sa53 00110101 350000h-35ffffh 128 64 sa54 00110110 360000h-36ffffh 128 64 sa55 00110111 370000h-37ffffh 128 64 sa56 00111000 380000h-38ffffh 128 64 sa57 00111001 390000h-39ffffh 128 64 sa58 00111010 3a0000h-3affffh 128 64 sa59 00111011 3b0000h-3bffffh 128 64 sa60 00111100 3c0000h-3cffffh 128 64 sa61 00111101 3d0000h-3dffffh 128 64 sa62 00111110 3e0000h-3effffh 128 64 sa63 00111111 3f0000h-3fffffh 128 64 sa64 01000000 400000h-40ffffh 128 64 sa65 01000001 410000h-41ffffh 128 64 sa66 01000010 420000h-42ffffh 128 64 sa67 01000011 430000h-43ffffh 128 64 sa68 01000100 440000h-44ffffh 128 64 sa69 01000101 450000h-45ffffh 128 64 sa70 01000110 460000h-46ffffh 128 64 sa71 01000111 470000h-47ffffh 128 64 sa72 01001000 480000h-48ffffh 128 64 sa73 01001001 490000h-49ffffh 128 64 sa74 01001010 4a0000h-4affffh 128 64 sa75 01001011 4b0000h-4bffffh 128 64 sa76 01001100 4c0000h-4cffffh 128 64 sa77 01001101 4d0000h-4dffffh www.datasheet.in 9 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l sector size sector sector address a23-a16 (x16) address range kbytes kwords 128 64 sa78 01001110 4e0000h-4effffh 128 64 sa79 01001111 4f0000h-4fffffh 128 64 sa80 01010000 500000h-50ffffh 128 64 sa81 01010001 510000h-51ffffh 128 64 sa82 01010010 520000h-52ffffh 128 64 sa83 01010011 530000h-53ffffh 128 64 sa84 01010100 540000h-54ffffh 128 64 sa85 01010101 550000h-55ffffh 128 64 sa86 01010110 560000h-56ffffh 128 64 sa87 01010111 570000h-57ffffh 128 64 sa88 01011000 580000h-58ffffh 128 64 sa89 01011001 590000h-59ffffh 128 64 sa90 01011010 5a0000h-5affffh 128 64 sa91 01011011 5b0000h-5bffffh 128 64 sa92 01011100 5c0000h-5cffffh 128 64 sa93 01011101 5d0000h-5dffffh 128 64 sa94 01011110 5e0000h-5effffh 128 64 sa95 01011111 5f0000h-5fffffh 128 64 sa96 01100000 600000h-60ffffh 128 64 sa97 01100001 610000h-61ffffh 128 64 sa98 01100010 620000h-62ffffh 128 64 sa99 01100011 630000h-63ffffh 128 64 sa100 01100100 640000h-64ffffh 128 64 sa101 01100101 650000h-65ffffh 128 64 sa102 01100110 660000h-66ffffh 128 64 sa103 01100111 670000h-67ffffh 128 64 sa104 01101000 680000h-68ffffh 128 64 sa105 01101001 690000h-69ffffh 128 64 sa106 01101010 6a0000h-6affffh 128 64 sa107 01101011 6b0000h-6bffffh 128 64 sa108 01101100 6c0000h-6cffffh 128 64 sa109 01101101 6d0000h-6dffffh 128 64 sa110 01101110 6e0000h-6effffh 128 64 sa111 01101111 6f0000h-6fffffh 128 64 sa112 01110000 700000h-70ffffh 128 64 sa113 01110001 710000h-71ffffh 128 64 sa114 01110010 720000h-72ffffh 128 64 sa115 01110011 730000h-73ffffh 128 64 sa116 01110100 740000h-74ffffh 128 64 sa117 01110101 750000h-75ffffh www.datasheet.in 10 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l sector size sector sector address a23-a16 (x16) address range kbytes kwords 128 64 sa118 01110110 760000h-76ffffh 128 64 sa119 01110111 770000h-77ffffh 128 64 sa120 01111000 780000h-78ffffh 128 64 sa121 01111001 790000h-79ffffh 128 64 sa122 01111010 7a0000h-7affffh 128 64 sa123 01111011 7b0000h-7bffffh 128 64 sa124 01111100 7c0000h-7cffffh 128 64 sa125 01111101 7d0000h-7dffffh 128 64 sa126 01111110 7e0000h-7effffh 128 64 sa127 01111111 7f0000h-7fffffh 128 64 sa128 10000000 800000h-80ffffh 128 64 sa129 10000001 810000h-81ffffh 128 64 sa130 10000010 820000h-82ffffh 128 64 sa131 10000011 830000h-83ffffh 128 64 sa132 10000100 840000h-84ffffh 128 64 sa133 10000101 850000h-85ffffh 128 64 sa134 10000110 860000h-86ffffh 128 64 sa135 10000111 870000h-87ffffh 128 64 sa136 10001000 880000h-88ffffh 128 64 sa137 10001001 890000h-89ffffh 128 64 sa138 10001010 8a0000h-8affffh 128 64 sa139 10001011 8b0000h-8bffffh 128 64 sa140 10001100 8c0000h-8cffffh 128 64 sa141 10001101 8d0000h-8dffffh 128 64 sa142 10001110 8e0000h-8effffh 128 64 sa143 10001111 8f0000h-8fffffh 128 64 sa144 10010000 900000h-90ffffh 128 64 sa145 10010001 910000h-91ffffh 128 64 sa146 10010010 920000h-92ffffh 128 64 sa147 10010011 930000h-93ffffh 128 64 sa148 10010100 940000h-94ffffh 128 64 sa149 10010101 950000h-95ffffh 128 64 sa150 10010110 960000h-96ffffh 128 64 sa151 10010111 970000h-97ffffh 128 64 sa152 10011000 980000h-98ffffh 128 64 sa153 10011001 990000h-99ffffh 128 64 sa154 10011010 9a0000h-9affffh 128 64 sa155 10011011 9b0000h-9bffffh 128 64 sa156 10011100 9c0000h-9cffffh 128 64 sa157 10011101 9d0000h-9dffffh 128 64 sa158 10011110 9e0000h-9effffh 128 64 sa159 10011111 9f0000h-9fffffh www.datasheet.in 11 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l sector size sector sector address a23-a16 (x16) address range kbytes kwords 128 64 sa160 10100000 a00000h-a0ffffh 128 64 sa161 10100001 a10000h-a1ffffh 128 64 sa162 10100010 a20000h-a2ffffh 128 64 sa163 10100011 a30000h-a3ffffh 128 64 sa164 10100100 a40000h-a4ffffh 128 64 sa165 10100101 a50000h-a5ffffh 128 64 sa166 10100110 a60000h-a6ffffh 128 64 sa167 10100111 a70000h-a7ffffh 128 64 sa168 10101000 a80000h-a8ffffh 128 64 sa169 10101001 a90000h-a9ffffh 128 64 sa170 10101010 aa0000h-aaffffh 128 64 sa171 10101011 ab0000h-abffffh 128 64 sa172 10101100 ac0000h-acffffh 128 64 sa173 10101101 ad0000h-adffffh 128 64 sa174 10101110 ae0000h-aeffffh 128 64 sa175 10101111 af0000h-afffffh 128 64 sa176 10110000 b00000h-b0ffffh 128 64 sa177 10110001 b10000h-b1ffffh 128 64 sa178 10110010 b20000h-b2ffffh 128 64 sa179 10110011 b30000h-b3ffffh 128 64 sa180 10110100 b40000h-b4ffffh 128 64 sa181 10110101 b50000h-b5ffffh 128 64 sa182 10110110 b60000h-b6ffffh 128 64 sa183 10110111 b70000h-b7ffffh 128 64 sa184 10111000 b80000h-b8ffffh 128 64 sa185 10111001 b90000h-b9ffffh 128 64 sa186 10111010 ba0000h-baffffh 128 64 sa187 10111011 bb0000h-bbffffh 128 64 sa188 10111100 bc0000h-bcffffh 128 64 sa189 10111101 bd0000h-bdffffh 128 64 sa190 10111110 be0000h-beffffh 128 64 sa191 10111111 bf0000h-bfffffh 128 64 sa192 11000000 c00000h-c0ffffh 128 64 sa193 11000001 c10000h-c1ffffh 128 64 sa194 11000010 c20000h-c2ffffh 128 64 sa195 11000011 c30000h-c3ffffh 128 64 sa196 11000100 c40000h-c4ffffh 128 64 sa197 11000101 c50000h-c5ffffh 128 64 sa198 11000110 c60000h-c6ffffh 128 64 sa199 11000111 c70000h-c7ffffh 128 64 sa200 11001000 c80000h-c8ffffh www.datasheet.in 12 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l sector size sector sector address a23-a16 (x16) address range kbytes kwords 128 64 sa201 11001001 c90000h-c9ffffh 128 64 sa202 11001010 ca0000h-caffffh 128 64 sa203 11001011 cb0000h-cbffffh 128 64 sa204 11001100 cc0000h-ccffffh 128 64 sa205 11001101 cd0000h-cdffffh 128 64 sa206 11001110 ce0000h-ceffffh 128 64 sa207 11001111 cf0000h-cfffffh 128 64 sa208 11010000 d00000h-d0ffffh 128 64 sa209 11010001 d10000h-d1ffffh 128 64 sa210 11010010 d20000h-d2ffffh 128 64 sa211 11010011 d30000h-d3ffffh 128 64 sa212 11010100 d40000h-d4ffffh 128 64 sa213 11010101 d50000h-d5ffffh 128 64 sa214 11010110 d60000h-d6ffffh 128 64 sa215 11010111 d70000h-d7ffffh 128 64 sa216 11011000 d80000h-d8ffffh 128 64 sa217 11011001 d90000h-d9ffffh 128 64 sa218 11011010 da0000h-daffffh 128 64 sa219 11011011 db0000h-dbffffh 128 64 sa220 11011100 dc0000h-dcffffh 128 64 sa221 11011101 dd0000h-ddffffh 128 64 sa222 11011110 de0000h-deffffh 128 64 sa223 11011111 df0000h-dfffffh 128 64 sa224 11100000 e00000h-e0ffffh 128 64 sa225 11100001 e10000h-e1ffffh 128 64 sa226 11100010 e20000h-e2ffffh 128 64 sa227 11100011 e30000h-e3ffffh 128 64 sa228 11100100 e40000h-e4ffffh 128 64 sa229 11100101 e50000h-e5ffffh 128 64 sa230 11100110 e60000h-e6ffffh 128 64 sa231 11100111 e70000h-e7ffffh 128 64 sa232 11101000 e80000h-e8ffffh 128 64 sa233 11101001 e90000h-e9ffffh 128 64 sa234 11101010 ea0000h-eaffffh 128 64 sa235 11101011 eb0000h-ebffffh 128 64 sa236 11101100 ec0000h-ecffffh 128 64 sa237 11101101 ed0000h-edffffh 128 64 sa238 11101110 ee0000h-eeffffh 128 64 sa239 11101111 ef0000h-efffffh 128 64 sa240 11110000 f00000h-f0ffffh www.datasheet.in 13 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l sector size sector sector address a23-a16 (x16) address range kbytes kwords 128 64 sa241 11110001 f10000h-f1ffffh 128 64 sa242 11110010 f20000h-f2ffffh 128 64 sa243 11110011 f30000h-f3ffffh 128 64 sa244 11110100 f40000h-f4ffffh 128 64 sa245 11110101 f50000h-f5ffffh 128 64 sa246 11110110 f60000h-f6ffffh 128 64 sa247 11110111 f70000h-f7ffffh 128 64 sa248 11111000 f80000h-f8ffffh 128 64 sa249 11111001 f90000h-f9ffffh 128 64 sa250 11111010 fa0000h-faffffh 128 64 sa251 11111011 fb0000h-fbffffh 128 64 sa252 11111100 fc0000h-fcffffh 128 64 sa253 11111101 fd0000h-fdffffh 128 64 sa254 11111110 fe0000h-feffffh 128 64 sa255 11111111 ff0000h-ffffffh www.datasheet.in 14 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l table 1-2: MX29GL128Eh/l sector group architecture sector size sector sector address a22-a16 (x16) address range kbytes kwords 128 64 sa0 0000000 000000h-00ffffh 128 64 sa1 0000001 010000h-01ffffh 128 64 sa2 0000010 020000h-02ffffh 128 64 sa3 0000011 030000h-03ffffh 128 64 sa4 0000100 040000h-04ffffh 128 64 sa5 0000101 050000h-05ffffh 128 64 sa6 0000110 060000h-06ffffh 128 64 sa7 0000111 070000h-07ffffh 128 64 sa8 0001000 080000h-08ffffh 128 64 sa9 0001001 090000h-09ffffh 128 64 sa10 0001010 0a0000h-0affffh 128 64 sa11 0001011 0b0000h-0bffffh 128 64 sa12 0001100 0c0000h-0cffffh 128 64 sa13 0001101 0d0000h-0dffffh 128 64 sa14 0001110 0e0000h-0effffh 128 64 sa15 0001111 0f0000h-0fffffh 128 64 sa16 0010000 100000h-10ffffh 128 64 sa17 0010001 110000h-11ffffh 128 64 sa18 0010010 120000h-12ffffh 128 64 sa19 0010011 130000h-13ffffh 128 64 sa20 0010100 140000h-14ffffh 128 64 sa21 0010101 150000h-15ffffh 128 64 sa22 0010110 160000h-16ffffh 128 64 sa23 0010111 170000h-17ffffh 128 64 sa24 0011000 180000h-18ffffh 128 64 sa25 0011001 190000h-19ffffh 128 64 sa26 0011010 1a0000h-1affffh 128 64 sa27 0011011 1b0000h-1bffffh 128 64 sa28 0011100 1c0000h-1cffffh 128 64 sa29 0011101 1d0000h-1dffffh 128 64 sa30 0011110 1e0000h-1effffh 128 64 sa31 0011111 1f0000h-1fffffh 128 64 sa32 0100000 200000h-20ffffh 128 64 sa33 0100001 210000h-21ffffh 128 64 sa34 0100010 220000h-22ffffh 128 64 sa35 0100011 230000h-23ffffh 128 64 sa36 0100100 240000h-24ffffh 128 64 sa37 0100101 250000h-25ffffh www.datasheet.in 15 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l sector size sector sector address a22-a16 (x16) address range kbytes kwords 128 64 sa38 0100110 260000h-26ffffh 128 64 sa39 0100111 270000h-27ffffh 128 64 sa40 0101000 280000h-28ffffh 128 64 sa41 0101001 290000h-29ffffh 128 64 sa42 0101010 2a0000h-2affffh 128 64 sa43 0101011 2b0000h-2bffffh 128 64 sa44 0101100 2c0000h-2cffffh 128 64 sa45 0101101 2d0000h-2dffffh 128 64 sa46 0101110 2e0000h-2effffh 128 64 sa47 0101111 2f0000h-2fffffh 128 64 sa48 0110000 300000h-30ffffh 128 64 sa49 0110001 310000h-31ffffh 128 64 sa50 0110010 320000h-32ffffh 128 64 sa51 0110011 330000h-33ffffh 128 64 sa52 0110100 340000h-34ffffh 128 64 sa53 0110101 350000h-35ffffh 128 64 sa54 0110110 360000h-36ffffh 128 64 sa55 0110111 370000h-37ffffh 128 64 sa56 0111000 380000h-38ffffh 128 64 sa57 0111001 390000h-39ffffh 128 64 sa58 0111010 3a0000h-3affffh 128 64 sa59 0111011 3b0000h-3bffffh 128 64 sa60 0111100 3c0000h-3cffffh 128 64 sa61 0111101 3d0000h-3dffffh 128 64 sa62 0111110 3e0000h-3effffh 128 64 sa63 0111111 3f0000h-3fffffh 128 64 sa64 1000000 400000h-40ffffh 128 64 sa65 1000001 410000h-41ffffh 128 64 sa66 1000010 420000h-42ffffh 128 64 sa67 1000011 430000h-43ffffh 128 64 sa68 1000100 440000h-44ffffh 128 64 sa69 1000101 450000h-45ffffh 128 64 sa70 1000110 460000h-46ffffh 128 64 sa71 1000111 470000h-47ffffh 128 64 sa72 1001000 480000h-48ffffh 128 64 sa73 1001001 490000h-49ffffh 128 64 sa74 1001010 4a0000h-4affffh 128 64 sa75 1001011 4b0000h-4bffffh 128 64 sa76 1001100 4c0000h-4cffffh 128 64 sa77 1001101 4d0000h-4dffffh www.datasheet.in 16 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l sector size sector sector address a22-a16 (x16) address range kbytes kwords 128 64 sa78 1001110 4e0000h-4effffh 128 64 sa79 1001111 4f0000h-4fffffh 128 64 sa80 1010000 500000h-50ffffh 128 64 sa81 1010001 510000h-51ffffh 128 64 sa82 1010010 520000h-52ffffh 128 64 sa83 1010011 530000h-53ffffh 128 64 sa84 1010100 540000h-54ffffh 128 64 sa85 1010101 550000h-55ffffh 128 64 sa86 1010110 560000h-56ffffh 128 64 sa87 1010111 570000h-57ffffh 128 64 sa88 1011000 580000h-58ffffh 128 64 sa89 1011001 590000h-59ffffh 128 64 sa90 1011010 5a0000h-5affffh 128 64 sa91 1011011 5b0000h-5bffffh 128 64 sa92 1011100 5c0000h-5cffffh 128 64 sa93 1011101 5d0000h-5dffffh 128 64 sa94 1011110 5e0000h-5effffh 128 64 sa95 1011111 5f0000h-5fffffh 128 64 sa96 1100000 600000h-60ffffh 128 64 sa97 1100001 610000h-61ffffh 128 64 sa98 1100010 620000h-62ffffh 128 64 sa99 1100011 630000h-63ffffh 128 64 sa100 1100100 640000h-64ffffh 128 64 sa101 1100101 650000h-65ffffh 128 64 sa102 1100110 660000h-66ffffh 128 64 sa103 1100111 670000h-67ffffh 128 64 sa104 1101000 680000h-68ffffh 128 64 sa105 1101001 690000h-69ffffh 128 64 sa106 1101010 6a0000h-6affffh 128 64 sa107 1101011 6b0000h-6bffffh 128 64 sa108 1101100 6c0000h-6cffffh 128 64 sa109 1101101 6d0000h-6dffffh 128 64 sa110 1101110 6e0000h-6effffh 128 64 sa111 1101111 6f0000h-6fffffh 128 64 sa112 1110000 700000h-70ffffh 128 64 sa113 1110001 710000h-71ffffh 128 64 sa114 1110010 720000h-72ffffh 128 64 sa115 1110011 730000h-73ffffh 128 64 sa116 1110100 740000h-74ffffh 128 64 sa117 1110101 750000h-75ffffh www.datasheet.in 17 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l sector size sector sector address a22-a16 (x16) address range kbytes kwords 128 64 sa118 1110110 760000h-76ffffh 128 64 sa119 1110111 770000h-77ffffh 128 64 sa120 1111000 780000h-78ffffh 128 64 sa121 1111001 790000h-79ffffh 128 64 sa122 1111010 7a0000h-7affffh 128 64 sa123 1111011 7b0000h-7bffffh 128 64 sa124 1111100 7c0000h-7cffffh 128 64 sa125 1111101 7d0000h-7dffffh 128 64 sa126 1111110 7e0000h-7effffh 128 64 sa127 1111111 7f0000h-7fffffh www.datasheet.in 18 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l table 2-1. bus operation notes: 1. the frst or last sector was protected if wp#/acc=vil. 2. when wp#/acc = vih, the protection conditions of the outmost sector depends on previous protection condi - tions. refer to the advaned protect feature. 3. q0~q15 are input (din) or output (dout) pins according to the requests of command sequence, sector pro - tection, or data polling algorithm. 4. in word mode (byte#=vih), the addresses are am to a0, am: msb of address. in byte mode (byte#=vil), the addresses are am to a-1 (q15), am: msb of address. mode select re- set# ce# we# oe# address (note4) data i/o q0~q7 byte# wp#/ acc vil vih data (i/o) q8~q15 device reset l x x x x highz highz highz l/h standby mode vcc 0.3v vcc 0.3v x x x highz highz highz h output disable h l h h x highz highz highz l/h read mode h l h l ain dout q8-q14= highz, q15=a1 dout l/h write h l l h ain din din note1,2 accelerate program h l l h ain din din vhv bus operation www.datasheet.in 19 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l notes: 1. sector unprotected code:00h. sector protected code:01h. 2. factory locked code: wp# protects high address sector: 99h. wp# protects low address sector: 89h factory unlocked code: wp# protects high address sector: 19h. wp# protects low address sector: 09h 3. am: msb of address. table 2-2. bus operation item control input am to a12 a11 to a10 a9 a8 to a7 a6 a5 to a4 a3 to a2 a1 a0 q0 ~ q7 q8 ~ q15 ce# we# oe# sector lock status verifcation l h l sa x v hv x l x l h l 01h or 00h (note 1) x read silicon id manufacturer code l h l x x v hv x l x l l l c2h x read silicon id -- mx29gl256e h/l cycle 1 l h l x x v hv x l x l l h 7eh 22h(word), xxh(byte) cycle 2 l h l x x v hv x l x h h l 22h 22h(word), xxh(byte) cycle 3 l h l x x v hv x l x h h h 01h 22h(word), xxh(byte) read silicon id -- MX29GL128E h/l cycle 1 l h l x x v hv x l x l l h 7eh 22h(word), xxh(byte) cycle 2 l h l x x v hv x l x h h l 21h 22h(word), xxh(byte) cycle 3 l h l x x v hv x l x h h h 01h 22h(word), xxh(byte) www.datasheet.in 20 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l functional operation description read operation to perform a read operation, the system addresses the desired memory array or status register location by pro - viding its address on the address pins and simultaneously enabling the chip by driving ce# & oe# low, and we# high. after the tce and toe timing requirements have been met, the system can read the contents of the addressed location by reading the data (i/o) pins. if either the ce# or oe# is held high, the outputs will remain tri-stated and no data will appear on the output pins. page read this device is able to conduct mxic maskrom compatible high performance page read. page size is 16 bytes or 8 words. the higher address amax ~ a3 select the certain page, while a2~a0 for word mode, a2~a-1 for byte mode select the particular word or byte in a page. the page access time is taa or tce, following by tpa for the rest of the page read time. when ce# toggles, access time is taa or tce. page mode can be turned on by keeping "page-read address" constant and changing the "intra-read page" addresses. write operation to perform a write operation, the system provides the desired address on the address pins, enables the chip by asserting ce# low, and disables the data (i/o) pins by holding oe# high. the system then places data to be written on the data (i/o) pins and pulses we# low. the device captures the address information on the falling edge of we# and the data on the rising edge of we#. to see an example, please refer to the timing diagram in figure 1 on page 49. the system is not allowed to write invalid commands (commands not defned in this datasheet) to the device. writing an invalid command may put the device in an undefned state. device reset driving the reset# pin low for a period of trp or more will return the device to read mode. if the device is in the middle of a program or erase operation, the reset operation will take at most a period of tready1 before the device returns to read mode. until the device does returns to read mode, the ry/by# pin will remain low (busy status). when the reset# pin is held at gnd0.3v, the device only consumes standby (isbr) current. however, the de - vice draws larger current if the reset# pin is held at a voltage greater than gnd+0.3v and less than or equal to vil. it is recommended to tie the system reset signal to the reset# pin of the fash memory. this allows the device to be reset with the system and puts it in a state where the system can immediately begin reading boot code from it. standby mode the device enters standby mode whenever the reset# and ce# pins are both held high except in the embed - ded mode. while in this mode, we# and oe# will be ignored, all data output pins will be in a high impedance state, and the device will draw minimal (isb) current. www.datasheet.in 21 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l functional operation description (cont'd) output disable while in active mode (reset# high and ce# low), the oe# pin controls the state of the output pins. if oe# is held high, all data (i/o) pins will remain tri-stated. if held low, the byte or word data (i/o) pins will drive data. byte/word selection the byte# input pin is used to select the organization of the array data and how the data is input/output on the data (i/o) pins. if the byte# pin is held high, word mode will be selected and all 16 data lines (q0 to q15) will be active. if byte# is forced low, byte mode will be active and only data lines q0 to q7 will be active. data lines q8 to q14 will remain in a high impedance state and q15 becomes the a-1 address input pin. hardware write protect by driving the wp#/acc pin low. the highest or lowest was protected from all erase/program operations. if wp#/acc is held high (vih to vcc), these sectors revert to their previously protected/unprotected status. accelerated programming operation by applying high voltage (vhv) to the wp#/acc pin, the device will enter the accelerated programming mode. this mode permits the system to skip the normal command unlock sequences and program byte/word locations directly. during accelerated programming, the current drawn from the wp#/acc pin is no more than icp1. write buffer programming operation programs 64bytes/32words in a programming operation. to trigger the write buffer programming, start by the frst two unlock cycles, then third cycle writes the write buffer load command at the destined programming sec - tor address. the forth cycle writes the "word locations subtract one" number. following above operations, system starts to write the mingling of address and data. after the programming of the frst address or data, the "write-buffer-page" is selected. the following data should be within the above men - tioned page. the "write-buffer-page" is selected by choosing address amax-a5. "write-buffer-page" address has to be the same for all address/ data write into the write buffer. if not, operation will abort. to program the content of the write buffer page this command must be followed by a write to buffer program con - frm command. the operation of write-buffer can be suspended or resumed by the standard commands, once the write buffer programming operation is fnished, itll return to normal read mode. www.datasheet.in 22 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l functional operation description (cont'd) write buffer programming operation (cont'd) abort will be executed for the write buffer programming sequence if following condition occurs: ? the value loaded is bigger than the page buffer size during "number of locations to program" ? address written in a sector is not the same as the one assigned during the write-buffer-load command. ? address/ data pair written to a different write-buffer-page than the one assigned by the "starting address" during the "write buffer data loading" operation. ? writing not "confrm command" after the assigned number of "data load" cycles. the abort is triggered by q1=1, q7=data# (last address written), q6=toggle, q5=0. a write-to-buffer-abort re - set command sequence has to be written to reset the device for the next operation. write buffer programming can be conducted in any sequence. however the cfi functions, autoselect, secured silicon sector are not functional when program operation is in progress. multiple write buffer programming opera - tions on the same write buffer address range without intervening erases is available. any bit in a write buffer ad - dress range cant be programmed from 0 back to 1. sector protect operation the device provides user programmable protection operations for selected sectors. please refer to table 1 which show all sector assignments. during the protection operation, the sector address of any sector may be used to specify the sector being pro - tected. automatic select bus operations the following fve bus operations require a9 to be raised to vhv. please see automatic select command sequence in the command operations section for details of equivalent command operations that do not require the use of vhv. sector lock status verification to determine the protected state of any sector using bus operations, the system performs a read operation with a9 raised to vhv, the sector address applied to address pins a22 to a12, address pins a6, a3, a2 & a0 held low, and address pin a1 held high. if data bit q0 is low, the sector is not protected, and if q0 is high, the sector is protected. www.datasheet.in 23 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l functional operation description (cont'd) read silicon id manufacturer code to determine the silicon id manufacturer code, the system performs a read operation with a9 raised to vhv and address pins a6, a3, a2, a1, & a0 held low. the macronix id code of c2h should be present on data bits q0 to q7. read indicator bit (q7) for security sector to determine if the security sector has been locked at the factory, the system performs a read operation with a9 raised to vhv, address pin a6, a3 & a2 held low, and address pins a1 & a0 held high. if the security sector has been locked at the factory, the code 99h(h)/89h(l) will be present on data bits q0 to q7. otherwise, the factory unlocked code of 19h(h)/09h(l) will be present. inherent data protection to avoid accidental erasure or programming of the device, the device is automatically reset to read mode during power up. additionally, the following design features protect the device from unintended data corruption. command completion only after the successful completion of the specifed command sets will the device begin its erase or program operation. the failure in observing valid command sets will result in the memory returning to read mode. low vcc write inhibit the device refuses to accept any write command when vcc is less than vlko. this prevents data from spuriously being altered during power-up, power-down, or temporary power interruptions. the device automatically resets itself when vcc is lower than vlko and write cycles are ignored until vcc is greater than vlko. the system must provide proper signals on control pins after vcc rises above vlko to avoid unintentional program or erase operations. write pulse "glitch" protection ce#, we#, oe# pulses shorter than 5ns are treated as glitches and will not be regarded as an effective write cycle. logical inhibit a valid write cycle requires both ce# and we# at vil with oe# at vih. write cycle is ignored when either ce# at vih, we# at vih, or oe# at vil. www.datasheet.in 24 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l functional operation description (cont'd) power-up sequence upon power up, the device is placed in read mode. furthermore, program or erase operation will begin only after successful completion of specifed command sequences. power-up write inhibit when we#, ce# is held at vil and oe# is held at vih during power up, the device ignores the frst command on the rising edge of we#. power supply decoupling a 0.1uf capacitor should be connected between the vcc and gnd to reduce the noise effect. www.datasheet.in 25 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l command operations reading the memory array read mode is the default state after power up or after a reset operation. to perform a read operation, please re - fer to read operation in the bus operations section above. if the device receives an erase suspend command while in the sector erase state, the erase operation will pause (after a time delay not exceeding 20us) and the device will enter erase-suspended read mode. while in the erase-suspended read mode, data can be programmed or read from any sector not being erased. reading from addresses within sector(s) being erased will only return the contents of the status register, which is in fact how the current status of the device can be determined. if a program command is issued to any inactive (not currently being erased) sector during erase-suspended read mode, the device will perform the program operation and automatically return to erase-suspended read mode after the program operation completes successfully. while in erase-suspended read mode, an erase resume command must be issued by the system to reactivate the erase operation. the erase operation will resume from where is was suspended and will continue until it completes successfully or another erase suspend command is received. after the memory device completes an embedded operation (automatic chip erase, sector erase, or program) successfully, it will automatically return to read mode and data can be read from any address in the array. if the embedded operation fails to complete, as indicated by status register bit q5 (exceeds time limit fag) going high during the operations, the system must perform a reset operation to return the device to read mode. there are several states that require a reset operation to return to read mode: 1. a program or erase failure--indicated by status register bit q5 going high during the operation. failures dur - ing either of these states will prevent the device from automatically returning to read mode. 2. the device is in auto select mode or cfi mode. these two states remain active until they are terminated by a reset operation. in the two situations above, if a reset operation (either hardware reset or software reset command) is not per - formed, the device will not return to read mode and the system will not be able to read array data. automatic programming of the memory array the device provides the user the ability to program the memory array in byte mode or word mode. as long as the users enters the correct cycle defned in the table 3 (including 2 unlock cycles and the a0h program com - mand), any byte or word data provided on the data lines by the system will automatically be programmed into the array at the specifed location. after the program command sequence has been executed, the internal write state machine (wsm) automatically executes the algorithms and timings necessary for programming and verifcation, which includes generating suit - able program pulses, checking cell threshold voltage margins, and repeating the program pulse if any cells do not pass verifcation or have low margins. the internal controller protects cells that do pass verifcation and mar - gin tests from being over-programmed by inhibiting further program pulses to these passing cells as weaker cells continue to be programmed. with the internal wsm automatically controlling the programming process, the user only needs to enter the pro - gram command and data once. www.datasheet.in 26 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l command operations (cont'd) automatic programming of the memory array (cont'd) programming will only change the bit status from "1" to "0". it is not possible to change the bit status from "0" to "1" by programming. this can only be done by an erase operation. furthermore, the internal write verifcation only checks and detects errors in cases where a "1" is not successfully programmed to "0". any commands written to the device during programming will be ignored except hardware reset or program sus - pend. hard ware reset will terminate the program operation after a period of time no more than 10us. when the embedded program algorithm is complete or the program operation is terminated by a hardware reset, the de - vice will return to read mode. program suspend ready, the device will enter program suspend read mode. after the embedded program operation has begun, the user can check for completion by reading the following bits in the status register: note: ry/by# is an open drain output pin and should be connected to vcc through a high value pull-up resistor. erasing the memory array there are two types of erase operations performed on the memory array -- sector erase and chip erase. in the sector erase operation, one or more selected sectors may be erased simultaneously. in the chip erase operation, the complete memory array is erased except for any protected sectors. more details of the protected sectors are explained in section 5. sector erase the sector erase operation is used to clear data within a sector by returning all of its memory locations to the "1" state. it requires six command cycles to initiate the erase operation. the frst two cycles are "unlock cycles", the third is a confguration cycle, the fourth and ffth are also "unlock cycles", and the sixth cycle is the sector erase command. after the sector erase command sequence has been issued, an internal 50us time-out counter is started. until this counter reaches zero, additional sector addresses and sector erase commands may be is - sued thus allowing multiple sectors to be selected and erased simultaneously. after the 50us time-out counter has expired, no new commands will be accepted and the embedded sector erase operation will begin. note that the 50us timer-out counter is restarted after every erase command sequence. if the user enters any command other than sector erase or erase suspend during the time-out period, the erase operation will abort and the de - vice will return to read mode. after the embedded sector erase operation begins, all commands except erase suspend will be ignored. the only way to interrupt the operation is with an erase suspend command or with a hardware reset. the hardware reset will completely abort the operation and return the device to read mode. status q7 *1 q6 *1 q5 q1 ry/by# (note) in progress q7# toggling 0 0 0 exceed time limit q7# toggling 1 n/a 0 www.datasheet.in 27 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l command operations (cont'd) sector erase (cont'd) the system can determine the status of the embedded sector erase operation by the following methods: chip erase the chip erase operation is used erase all the data within the memory array. all memory cells containing a "0" will be returned to the erased state of "1". this operation requires 6 write cycles to initiate the action. the frst two cycles are "unlock" cycles, the third is a confguration cycle, the fourth and ffth are also "unlock" cycles, and the sixth cycle initiates the chip erase operation. during the chip erase operation, no other software commands will be accepted, but if a hardware reset is re - ceived or the working voltage is too low, that chip erase will be terminated. after chip erase, the chip will auto - matically return to read mode. the system can determine the status of the embedded chip erase operation by the following methods: *1: ry/by# is open drain output pin and should be connected to vcc through a high value pull-up resistor. note: 1. the q3 status bit is the 50us time-out indicator. when q3=0, the 50us time-out counter has not yet reached zero and a new sector erase command may be issued to specify the address of another sector to be erased. when q3=1, the 50us time-out counter has expired and the sector erase operation has already begun. erase suspend is the only valid command that may be issued once the embedded erase operation is underway. 2. ry/by# is open drain output pin and should be connected to vcc through a high value pull-up resistor. 3. when an attempt is made to erase only protected sector(s), the erase operation will abort thus preventing any data changes in the protected sector(s). q7 will output "0" and q6 will toggle briefy (100us or less) before aborting and returning the device to read mode. if unprotected sectors are also specifed, however, they will be erased normally and the protected sector(s) will remain unchanged. 4. q2 is a localized indicator showing a specifed sector is undergoing erase operation or not. q2 toggles when user reads at addresses where the sectors are actively being erased (in erase mode) or to be erased (in erase suspend mode). status q7 q6 q5 q3 *1 q2 ry/by# *2 time-out period 0 toggling 0 0 toggling 0 in progress 0 toggling 0 1 toggling 0 exceeded time limit 0 toggling 1 1 toggling 0 status q7 q6 q5 q2 ry/by# *1 in progress 0 toggling 0 toggling 0 exceed time limit 0 toggling 1 toggling 0 www.datasheet.in 28 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l after beginning a sector erase operation, erase suspend is the only valid command that may be issued. if sys - tem issues an erase suspend command during the 50us time-out period following a sector erase command, the time-out period will terminate immediately and the device will enter erase-suspended read mode. if the system issues an erase suspend command after the sector erase operation has already begun, the device will not enter erase-suspended read mode until 20us time has elapsed. the system can determine if the device has entered the erase-suspended read mode through q6, q7, and ry/by#. after the device has entered erase-suspended read mode, the system can read or program any sector(s) ex - cept those being erased by the suspended erase operation. reading any sector being erased or programmed will return the contents of the status register. whenever a suspend command is issued, user must issue a re - sume command and check q6 toggle bit status, before issue another erase command. the system can use the status register bits shown in the following table to determine the current state of the device: command operations (cont'd) erase suspend/resume when the device has suspended erasing, user can execute the command sets except sector erase and chip erase, such as read silicon id, sector protect verify, program, cfi query and erase resume. sector erase resume the sector erase resume command is valid only when the device is in erase-suspended read mode. after erase resumes, the user can issue another ease suspend command, but there should be a 400us interval be - tween ease resume and the next erase suspend command. status q7 q6 q5 q3 q2 q1 ry/by# erase suspend read in erase suspended sector 1 no toggle 0 n/a toggle n/a 1 erase suspend read in non-erase suspended sector data data data data data data 1 erase suspend program in non-erase suspended sector q7# toggle 0 n/a n/a n/a 0 www.datasheet.in 29 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l command operations (cont'd) program suspend/resume when the device has program/erase suspended, user can execute read array, auto-select, read cfi, read secu - rity silicon. program resume the program resume command is valid only when the device is in program-suspended mode. after program resumes, the user can issue another program suspend command, but there should be a 5us interval between program resume and the next program suspend command. status q7 q6 q5 q3 q2 q1 ry/by# program suspend read in program suspended sector invalid 1 program suspend read in non-program suspended sector data data data data data data 1 buffer write abort q1 is the indicator of buffer write abort. when q1=1, the device will abort from buffer write and go back to read status register shown as following table: status q7 q6 q5 q3 q2 q1 ry/by# buffer write busy q7# toggle 0 n/a n/a 0 0 buffer write abort q7# toggle 0 n/a n/a 1 0 buffer write exceeded time limit q7# toggle 1 n/a n/a 0 0 after beginning a program operation, program suspend is the only valid command that may be issued. the sys - tem can determine if the device has entered the program-suspended read mode through q6 and ry/by#. after the device has entered program-suspended mode, the system can read any sector(s) except those being programd by the suspended program operation. reading the sector being program suspended is invalid. when - ever a suspend command is issued, user must issue a resume command and check q6 toggle bit status, before issue another program command. the system can use the status register bits shown in the following table to de - termine the current state of the device: www.datasheet.in 30 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l automatic select operations when the device is in read mode, program suspended mode, erase-suspended read mode, or cfi mode, the user can issue the automatic select command shown in table 3 (two unlock cycles followed by the automatic select command 90h) to enter automatic select mode. after entering automatic select mode, the user can query the manufacturer id, device id, security sector locked status, or sector protected status multiple times without issuing a new automatic select command. while in automatic select mode, issuing a reset command (f0h) will return the device to read mode (or ease- suspended read mode if erase-suspend was active) or program suspended read mode if program suspend was active. another way to enter automatic select mode is to use one of the bus operations shown in table 2. bus operation_2. after the high voltage (vhv) is removed from the a9 pin, the device will automatically return to read mode or erase-suspended read mode. automatic select command sequence automatic select mode is used to access the manufacturer id, device id and to verify whether or not secured silicon is locked and whether or not a sector is protected. the automatic select mode has four command cycles. the frst two are unlock cycles, and followed by a specifc command. the fourth cycle is a normal read cycle, and user can read at any address any number of times without entering another command sequence. the reset command is necessary to exit the automatic select mode and back to read array. the following table shows the identifcation code with corresponding address. after entering automatic select mode, no other commands are allowed except the reset command. command operations (cont'd) address data (hex) representation manufacturer id word x00 c2 byte x00 c2 device id mx29gl256e word x01/0e/0f 227e/2222/2201 byte x02/1c/1e 7e/22/01 MX29GL128E word x01/0e/0f 227e/2221/2201 byte x02/1c/1e 7e/21/01 secured silicon word x03 99/19 (h) factory locked/unlocked 89/09 (l) byte x06 99/19 (h) factory locked/unlocked 89/09 (l) sector protect verify word (sector address) x 02 00/01 unprotected/protected byte (sector address) x 04 00/01 unprotected/protected www.datasheet.in 31 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l read manufacturer id or device id the manufacturer id (identifcation) is a unique hexadecimal number assigned to each manufacturer by the je - dec committee. each company has its own manufacturer id, which is different from the id of all other compa - nies. the number assigned to macronix is c2h. after entering automatic select mode, performing a read operation with a1 & a0 held low will cause the device to output the manufacturer id on the data i/o (q7 to q0) pins. reset in the following situations, executing reset command will reset device back to read mode: ? among erase command sequence (before the full command set is completed) ? sector erase time-out period ? erase fail (while q5 is high) ? among program command sequence (before the full command set is completed, erase-suspended program included) ? program fail (while q5 is high, and erase-suspended program fail is included) ? auto-select mode ? cfi mode while device is at the status of program fail or erase fail (q5 is high), user must issue reset command to reset device back to read array mode. while the device is in auto-select mode or cfi mode, user must issue reset command to reset device back to read array mode. when the device is in the progress of programming (not program fail) or erasing (not erase fail), device will ig - nore reset command. command operations (cont'd) www.datasheet.in 32 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l start q1=0 q2=0 password protection mode to choose protection mode set lock register bit (q1/q2) set spb lock bit spb = 0 spb = 1 spb lock bit unlocked spb is changeable solid write protect bit (spb) spb=0 sector protect spb=1 sector unprotect temporary unprotect spb bit (uspb) uspb=0 temp. unprotect spb bit, spb changeable uspb=1 spb bit can not changeable uspb 0 uspb 1 uspb 2 : : uspb n-1 uspb n spb 0 spb 1 spb 2 : : spb n-1 spb n sa 0 sa 1 sa 2 : : sa n-1 sa n dpb 0 dpb 1 dpb 2 : : dpb n-1 dpb n spb lock bit locked all spb can not changeable solid protection mode set 64 bit password sector array dynamic write protect bit (dpb) dpb=0 sector protect dpb=1 sector unprotect advanced sector protection/un-protection there are two ways to implement software advanced sector protection on this device: password method or solid methods. through these two protection method, user can disable or enable the programming or erasing operation to any individual sector or whole chip. the fgure below helps describe an overview of these methods. the device is default to the solid mode and all sectors are unprotected when shipped from factory. shows the detail algorithm of advance sector protecting. advance sector protection/unprotection spb program algorithm : www.datasheet.in 33 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l 1. lock register user can choose favorite sector protecting method via setting lock register bits q1 and q2. lock register is a 16-bit one-time programmable register. once programming either q1 or q2, they will be locked in that mode and the others will be disabled permanently. q1 and q2 can not be programmed at the same time, otherwise the device will abort the operation. if user selects password protection mode, the password setting is required. user can set password by issuing password program command. after the lock register bits command set entry command sequence is issued, the read and write operations for normal sectors are disabled until this mode exits. a lock register allows the memory sectors and extended memory sector protection to be confgured. lock register bits q15-q3 q2 q1 q0 don't care password protection mode lock bit solid protection mode lock bit secured silicon sector protection bit please refer to the command for lock register command set to read and program the lock register. lock register program algorithm : start pass exit lock register command done yes yes no q5 = 1 no write data aah, address 555h lock register command set entry write data 55h, address 2aah write data 40h, address 555h write data a0h, address don?t care write program data, address don?t care data # polling algorithm fail reset command lock register data program www.datasheet.in 34 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l 2. solid write (non-volatile) protection mode 2.1 solid write protection bits (spb) the solid write protection bit (spb) is a nonvolatile bit with the same endurances as the flash memory. it is assigned to each sector individually. the spb is preprogramming, and its verifcation prior to erasure are managed by the device, so system monitoring is not necessary. when a spb is set to 0, the associated sector is protected, preventing any program or erase operation on this sector. the spb bits are set individually by spb program command. however, it cannot be cleared individually. issuing the all spb erase command will erase all spb in the same time. during spb programming period, the read and write operations are disabled for normal sector until this mode exits. if one of the protected sector need to be unprotected (corresponding spb set to 1), a few more steps are required. first, the spb lock bit must be cleared by either putting the device through a power-cycle, or hardware reset. the spbs can then be changed to refect the desired settings. setting the spb lock bit once again locks the spbs, and the device operates normally again. to verify the programming state of the spb for a given sector, issuing a spb status read command to the device is required. refer to the fow chart below for details of spb program algorithm. notes 1. the read actions within that sector will bring the spb status back for that sector. all read actions must be executed by read mode. the specifc sector address is written as the program command at the same time. 2.once spb lock bit is set, its program or erase command will not be executed and times-out without programming or erasing the spb. 3. always issue exit command after the execution of resetting the device to read mode and re-enables read and write actions for normal array. 4. to achieve the best effect of protection, it is recommended to execute the spb lock bit set command early in the boot code and protect the boot code by holding wp#/acc = vil. note that the spb and dpb bits have the same function when wp#/acc = vhh, and it is same when acc =vih. 2.2 dynamic protection bits (dpbs) the dynamic protection allows the software application to easily protect sectors against inadvertent change. however, the protection can be easily disabled when changes are necessary. all dynamic protection bit (dpb) are volatile and assigned to each sector. it can be modify individual. dpbs provide the protection scheme only for unprotected sectors that have their spbs cleared (erase can be individually modifed d to 1).to modify the dpb status by issuing the dpb set (programmed to 0) or dpb clear (erased to 1)commands, then placing each sector in the protected or unprotected state seperately. after the dpb clear command is issued(erased to 1), the sector may be modifed depending on the spb state of that sector when the parts are frst shipped, the spbs are cleared (erased to 1) and upon power up or reset, the dpbs can be set or cleared depending upon the ordering option chosen. www.datasheet.in 35 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l 2.3 temporary un-protect solid write protect bit (uspb) temporary un-protect solid write protect bits are volatile and unique for each sector and can be individually modifed. by issuing the uspb set or clear command sequences, the uspbs are set (programmed to 0) or cleared (erased to 1), thus mask each sector's solid write protect bit property. this feature allows software to temp unprotect write protect sectors despite of spb's property when dpbs are cleared. notes: 1. the uspbs can be set (programmed to 0) or cleared (erased to 1) as often as needed. the uspbs are cleared (all 1s) upon power up. hardware reset wont change uspbs/dpbs status. the sectors spbs would be in effective state after power up is chosen. 2. however, if there is a need to write a solid protect bit protect sector status, user don't have to clear all spb bits. they just use software to set corresponding uspb to 0, which guarantees that corresponding dpb status is clear, and original solid protect bit protected sectors can be temporary written. 3. spblk should be cleared to modify uspb status. q6 toggle ? q6 toggle ? q5 = 1 ? no no yes no no spb command set entry program spb read q7~q0 twice read q7~q0 twice read q7~q0 twice yes yes yes wait 500 ?s program fail write reset cmd pass q0= '1' (erase) '0' (program) spb command set exit note: spb program/ erase status polling fowchart: check q6 toggle, when q6 stop toggle, the read status is 00h /01h (00h for program/ 01h for erase), otherwise the status is fail and exit. spb program algorithm : www.datasheet.in 36 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l 4. password protection method the security level of password protection method is higher then the solid protection mode. the 64 bit password is requested before modify spb lock bit status. when device is under password protection mode, the spb lock bit is set 0, after a power-up cycle or reset command. a correct password is required for password unlock command, to unlock the spb lock bit. await 2us is necessary to unlocked the device after valid password is given. after that, the spb bits are allows to be changed. the password unlock command are issued slower then 2 s every time,. to prevent hacker from trying all the 64-bit password combinations. to place the device in password protection mode, a few more steps are required. first, prior to entering the password protection mode, it is necessary to set a 64-bit password to verify it. password verifcation is only allowed during the password programming operation. second, the password protection mode is then activated by programming the password the password protection mode lock bit to0. this operation is not reversible. once the bit is programmed, it cannot be erased, and the device remains permanently in password protection mode, and the 64-bit password can neither be retrieved nor reprogrammed. moreover, all commands to the address where the password is stored are disabled. the password is all 1s when shipped from the factory, it is only capable to programming "0"s under password program command. all 64-bit password combinations are valid as a password. no special address is required for programming the password. in order to prevent access, the password mode locking bit must be set after the password is programmed and verifed. once the password mode lock bit is set, prevents reading 64-bits password on the data bus and any future modifcation. there is no means to verify what the password is after it is set. entry command sequence will cause the read and write operation to be disabled for normal sector until this mode exits. once sector under protected status, device will ignores the program/erase command, enable status polling and returns to read mode without contents change. the dpb, spb,uspb and spb lock bit status of each sector can be verifed by issue status read commands. 3. solid protection bit lock bit the solid protection bit lock bit (spb) is assign to control all spb status. it is a unique and volatile. when spb=0 (set), all spbs are locked and can not be changed. when spb=1 (cleared), all spbs are unlock and allows to be changed. there is no software command sequence requested to unlocks this bit, unless the device is in the password protection mode. to clear the spb lock bit, just take the device through a hardware reset or a power-up cycle. in order to prevent moifed, the spb lock bit must be set (spb=0) after all spbs are setting the desired status. www.datasheet.in 37 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l sector protection status table protection bit status sector status dpb spblk spb uspb clear clear clear clear unprotect, dpb/spb/uspb are changeable clear clear clear set unprotect, dpb/spb/uspb are changeable clear clear set clear protect, dpb/spb/uspb are changeable clear clear set set unprotect, dpb/spb/uspb are changeable clear set clear clear unprotect, dpb/uspb are changeable clear set clear set unprotect, dpb/uspb are changeable clear set set clear protect, dpb/uspb are changeable clear set set set unprotect, dpb/uspb are changeable set clear clear clear protect, dpb/spb/uspb are changeable set clear clear set protect, dpb/spb/uspb are changeable set clear set clear protect, dpb/spb/uspb are changeable set clear set set protect, dpb/spb/uspb are changeable set set clear clear protect, dpb/uspb are changeable set set clear set protect, dpb/uspb are changeable set set set clear protect, dpb/uspb are changeable set set set set protect, dpb/uspb are changeable www.datasheet.in 38 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l secured silicon sector address range standard factory locked express flash factory locked customer lockable 000000h-000007h esn esn or determined by customer determined by customer 000008h-00007fh unavailable determined by customer customer lockable: security sector not programmed or protected at the factory when the security feature is not required, the security region can act as an extra memory space. security silicon sector can also be protected by two methods. note that once the security silicon sector is pro - tected, there is no way to unprotect the security silicon sector and the content of it can no longer be altered. after the security silicon is locked and verifed, system must write exit security sector region, go through a pow - er cycle, or issue a hardware reset to return the device to read normal array mode. security sector flash memory region the security sector region is an extra otp memory space of 128 words in length. the security sector can be locked upon shipping from factory, or it can be locked by customer after shipping. customer can issue security sector factory protect verify and/or security sector protect verify to query the lock status of the device. in factory-locked device, security sector region is protected when shipped from factory and the security silicon sector indicator bit is set to "1". in customer lockable device, security sector region is unprotected when shipped from factory and the security silicon indicator bit is set to "0". factory locked: security sector programmed and protected at the factory in a factory locked device, the security sector is permanently locked before shipping from the factory. the de - vice will have a 16-byte (8-word) esn in the security region. the esn occupies addresses 00000h to 0000fh in byte mode or 00000h to 00007h in word mode. www.datasheet.in 39 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l table 3. command definitions wa= write address wd= write data sa= sector address n-1= word count wbl= write buffer location pwd= password pwdn=password word 0, word 1, word n id1/id2/id3: refer to table 2-2 for detail id of each device. comm- and read mode reset mode automatic select security sector region exit security sector silicon id device id factory protect verify sector protect verify word byte word byte word byte word byte word byte word byte 1st bus cycle addr addr xxx 555 aaa 555 aaa 555 aaa 555 aaa 555 aaa 555 aaa data data f0 aa aa aa aa aa aa aa aa aa aa aa aa 2nd bus cycle addr 2aa 555 2aa 555 2aa 555 2aa 555 2aa 555 2aa 555 data 55 55 55 55 55 55 55 55 55 55 55 55 3rd bus cycle addr 555 aaa 555 aaa 555 aaa 555 aaa 555 aaa 555 aaa data 90 90 90 90 90 90 90 90 88 88 90 90 4th bus cycle addr x00 x00 x01 x02 x03 x06 (sector) x02 (sector) x04 xxx xxx data c2h c2h id1 id1 99/19(h) 89/09(l) 00/01 00/01 00 00 5th bus cycle addr x0e x1c data id2 id2 6th bus cycle addr x0f x1e data id3 id3 comm- and program write to buffer program write to buffer program abort reset write to buffer program confrm chip erase sector erase cfi read program/ erase suspend program/ erase resume word byte word byte word byte word byte word byte word byte word byte word byte word byte 1st bus cycle addr 555 aaa 555 aaa 555 aaa sa sa 555 aaa 555 aaa 55 aa xxx xxx xxx xxx data aa aa aa aa aa aa 29 29 aa aa aa aa 98 98 b0 b0 30 30 2nd bus cycle addr 2aa 555 2aa 555 2aa 555 2aa 555 2aa 555 data 55 55 55 55 55 55 55 55 55 55 3rd bus cycle addr 555 aaa sa sa 555 aaa 555 aaa 555 aaa data a0 a0 25 25 f0 f0 80 80 80 80 4th bus cycle addr addr addr sa sa 555 aaa 555 aaa data data data n-1 n-1 aa aa aa aa 5th bus cycle addr wa wa 2aa 555 2aa 555 data wd wd 55 55 55 55 6th bus cycle addr wbl wbl 555 aaa sec- tor sec- tor data wd wd 10 10 30 30 www.datasheet.in 40 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l command deep power down password protection enter exit password command set entry password program password read password unlock password command set exit word byte word byte word byte word byte word byte word byte word byte 1st bus cycle addr 555 aaa xxx xxx 555 aaa xxx xxx x00 x00 00 00 xxx xxx data aa aa ab ab aa aa a0 a0 pwd0 pwd0 25 25 90 90 2nd bus cycle addr 2aa 555 2aa 555 pwa pwa x01 x01 00 00 xxx xxx data 55 55 55 55 pwd pwd pwd1 pwd1 03 03 00 00 3rd bus cycle addr xxx xxx 555 aaa x02 x02 x00 x00 data b9 b9 60 60 pwd2 pwd2 pwd0 pwd0 4th bus cycle addr x03 x03 x01 x01 data pwd3 pwd3 pwd1 pwd1 5th bus cycle addr x04 x02 x02 data pwd4 pwd2 pwd2 6th bus cycle addr x05 x03 x03 data pwd5 pwd3 pwd3 7th bus cycle addr x06 00 x04 data pwd6 29 pwd4 8th bus cycle addr x07 x05 data pwd7 pwd5 9th bus cycle addr x06 data pwd6 10th bus cycle addr x07 data pwd7 11th bus cycle addr 00 data 29 www.datasheet.in 41 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l command lock register global non-volatile lock register command set entry program read lock register command set exit spb command set entry spb program all spb erase spb status read word byte word byte word byte word byte word byte word byte word byte word byte 1st bus cycle addr 555 aaa xxx xxx xxx xxx xxx xxx 555 aaa xxx xxx xxx xxx sa sa data aa aa a0 a0 data data 90 90 aa aa a0 a0 80 80 00/01 00/01 2nd bus cycle addr 2aa 555 xxx xxx xxx xxx 2aa 555 sa sa 00 00 data 55 55 data data 00 00 55 55 00 00 30 30 3rd bus cycle addr 555 aaa 555 aaa data 40 40 c0 c0 4th bus cycle addr data 5th bus cycle addr data command global non- volatile global volatile freeze volatile spb command set exit spb lock command set entry spb lock set spb lock status read spb lock command set exit dpb command set entry dpb set dpb clear word byte word byte word byte word byte word byte word byte word byte word byte 1st bus cycle addr xxx xxx 555 aaa xxx xxx xxx xxx xxx xxx 555 aaa xxx xxx xxx xxx data 90 90 aa aa a0 a0 00/01 00/01 90 90 aa aa a0 a0 a0 a0 2nd bus cycle addr xxx xxx 2aa 555 xxx xxx xxx xxx 2aa 555 sa sa sa sa data 00 00 55 55 00 00 00 00 55 55 00 00 01 01 3rd bus cycle addr 555 aaa 555 aaa data 50 50 e0 e0 4th bus cycle addr data 5th bus cycle addr data command volatile dpb status read dpb command set exit word byte word byte 1st bus cycle addr sa sa xxx xxx data 00/01 00/01 90 90 2nd bus cycle addr xxx xxx data 00 00 3rd bus cycle addr data 4th bus cycle addr data 5th bus cycle addr data notes: * it is not recommended to adopt any other code not in the command defnition table which will potentially enter the hidden mode. * for the spb lock and dpb status read "00" means lock (protect), "01" means unlock (unprotect). www.datasheet.in 42 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l table 4-1. cfi mode: identifcation data values (all values in these tables are in hexadecimal) table 4-2. cfi mode: system interface data values common flash memory interface (cfi) mode query command and command flash memory interface (cfi) mode the device features cfi mode. host system can retrieve the operating characteristics, structure and vendor- specifed information such as identifying information, memory size, byte/word confguration, operating voltages and timing information of this device by cfi mode. if the system writes the cfi query command "98h", to ad - dress "55h"/"aah" (depending on word/byte mode), the device will enter the cfi query mode, any time the de - vice is ready to read array data. the system can read cfi information at the addresses given in table 4. once user enters cfi query mode, user can issue reset command to exit cfi mode and return to read array mode. description address (h) (word mode) address (h) (byte mode) data (h) vcc supply minimum program/erase voltage 1b 36 0027 vcc supply maximum program/erase voltage 1c 38 0036 vpp supply minimum program/erase voltage 1d 3a 0000 vpp supply maximum program/erase voltage 1e 3c 0000 typical timeout per single word/byte write, 2 n us 1f 3e 0003 typical timeout for maximum-size buffer write, 2 n us (00h, not support) 20 40 0006 typical timeout per individual block erase, 2 n ms 21 42 0009 typical timeout for full chip erase, 2 n ms (00h, not support) 22 44 0013 maximum timeout for word/byte write, 2 n times typical 23 46 0003 maximum timeout for buffer write, 2 n times typical 24 48 0005 maximum timeout per individual block erase, 2 n times typical 25 4a 0003 maximum timeout for chip erase, 2 n times typical (00h, not support) 26 4c 0002 description address (h) (word mode) address (h) (byte mode) data (h) query-unique ascii string "qry" 10 20 0051 11 22 0052 12 24 0059 primary vendor command set and control interface id code 13 26 0002 14 28 0000 address for primary algorithm extended query table 15 2a 0040 16 2c 0000 alternate vendor command set and control interface id code 17 2e 0000 18 30 0000 address for alternate algorithm extended query table 19 32 0000 1a 34 0000 www.datasheet.in 43 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l table 4-3. cfi mode: device geometry data values description address (h) (word mode) address (h) (byte mode) data (h) device size = 2 n in number of bytes (19=256mb, 18=128mb) 27 4e 0019/ 0018 flash device interface description (02=asynchronous x8/x16) 28 50 0002 29 52 0000 maximum number of bytes in buffer write = 2 n (00h, not support) 2a 54 0006 2b 56 0000 number of erase regions within device (01h:uniform, 02h:boot) 2c 58 0001 index for erase bank area 1: [2e,2d] = # of same-size sectors in region 1-1 [30, 2f] = sector size in multiples of 256k-bytes 256mb=00ff, 0000, 0000, 0002 128mb=007f, 0000, 0000, 0002 2d 5a 00xx 2e 5c 0000 2f 5e 0000 30 60 0002 index for erase bank area 2 31 62 0000 32 64 0000 33 66 0000 34 68 0000 index for erase bank area 3 35 6a 0000 36 6c 0000 37 6e 0000 38 70 0000 index for erase bank area 4 39 72 0000 3a 74 0000 3b 76 0000 3c 78 0000 www.datasheet.in 44 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l table 4-4. cfi mode: primary vendor-specifc extended query data values description address (h) (word mode) address (h) (byte mode) data (h) query - primary extended table, unique ascii string, pri 40 80 0050 41 82 0052 42 84 0049 major version number, ascii 43 86 0031 minor version number, ascii 44 88 0033 unlock recognizes address (0= recognize, 1= don't recognize) 45 8a 0014 erase suspend (2= to both read and program) 46 8c 0002 sector protect (n= # of sectors/group) 47 8e 0001 temporary sector unprotect (1=supported) 48 90 0000 sector protect/chip unprotect scheme 49 92 0008 simultaneous r/w operation (0=not supported) 4a 94 0000 burst mode (0=not supported) 4b 96 0000 page mode (0=not supported, 01 = 4 word page, 02 = 8 word page) 4c 98 0002 minimum acc(acceleration) supply (0= not supported), [d7:d4] for volt, [d3:d0] for 100mv 4d 9a 0095 maximum acc(acceleration) supply (0= not supported), [d7:d4] for volt, [d3:d0] for 100mv 4e 9c 00a5 wp# protection 04=uniform sectors bottom wp# protect 05=uniform sectors top wp# protect 4f 9e 0004/ 0005 program suspend (0=not supported, 1=supported) 50 a0 0001 www.datasheet.in 45 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l absolute maximum stress ratings operating temperature and voltage electrical characteristics surrounding temperature with bias -65c to +125c storage temperature -65c to +150c voltage range vcc -0.5v to +4.0 v vi/o -0.5v to +4.0 v a9 , wp#/acc -0.5v to +10.5 v the other pins. -0.5v to vcc +0.5v output short circuit current (less than one second) 200 ma commercial (c) grade surrounding temperature (t a ) 0c to +70c industrial (i) grade surrounding temperature (t a ) -40c to +85c vcc supply voltages full vcc range +2.7 v to 3.6 v regulated vcc range +3.0 v to 3.6 v vi/o range +2.7 v to 3.6 v www.datasheet.in 46 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l dc characteristics symbol description min typ max remark iilk input leak 2.0ua iilk9 a9 leak 35ua a9=10.5v iolk output leak 1.0ua icr1 read current 6ma 20ma ce#=vil, oe#=vih, vcc=vccmax; f=1mhz, byte mode 30ma 50ma ce#=vil, oe#=vih, vcc=vccmax; f=5mhz, byte mode 60ma 100ma ce#=vil, oe#=vih, vcc=vccmax; f=10mhz iio v io non-active current 0.2ma 10ma icw write current 26ma 30ma ce#=vil, oe#=vih, we#=vil isb standby current 30ua 100ua vcc=vcc max, other pin disable isbr reset current 30ua 100ua vcc=vccmax, reset# enable, other pin disable isbs sleep mode current 30ua 100ua idpd vcc deep power down current 10ua icp1 accelerated pgm current, wp#/acc pin(word/byte) 5ma 10ma ce#=vil, oe#=vih icp2 accelerated pgm current, vcc pin, (word/byte) 20ma 30ma ce#=vil, oe#=vih vil input low voltage -0.1v 0.3xvi/o vih input high voltage 0.7xvi/o vi/o+0.3v vhv very high voltage for auto select/ accelerated program 9.5v 10.5v vol output low voltage 0.45v iol=100ua voh1 ouput high voltage 0.85xvi/o ioh1=-100ua voh2 ouput high voltage vi/o-0.4v ioh2=-100ua vlko low vcc lock-out voltage 2.3v 2.5v note: sleep mode enables the lower power when address remain stable for taa+30ns. www.datasheet.in 47 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l switching test circuits switching test waveforms test condition output load capacitance,cl : 1ttl gate, 30pf(90ns) rise/fall times : 5ns input pulse levels :0.0 ~ vi/o in/out reference levels :0.5v i/o t est p oints vi/o vi/o / 2 vi/o / 2 0.0v output input device under test cl 3.3v 6.2k 2.7k www.datasheet.in 48 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l ac characteristics- (1) symbol description 29gl256e (vcc=2.7v~3.6v) 29gl256e (vcc=3.0v~3.6v) unit min. typ. max. min. typ. max. taa valid data output after address 100 90 ns tpa page access time 25 25 ns tce valid data output after ce# low 100 90 ns toe valid data output after oe# low 25 25 ns tdf data output foating after oe# high 40 40 ns toh output hold time from the earliest rising edge of address,ce#, oe# 0 0 ns trc read period time 100 90 ns twc write period time 100 90 ns tcwc command write period time 100 90 ns tas address setup time 0 0 ns tah address hold time 45 45 ns tds data setup time 30 30 ns tdh data hold time 0 0 ns tvcs vcc setup time 500 500 us tcs chip enable setup time 0 0 ns tch chip enable hold time 0 0 ns toes output enable setup time 0 0 ns toeh output enable hold time read 0 0 ns toggle & data# polling 10 10 ns tws we# setup time 0 0 ns twh we# hold time 0 0 ns tcepw ce# pulse width 35 35 ns tcepwh ce# pulse width high 30 30 ns twp we# pulse width 35 35 ns twph we# pulse width high 30 30 ns tbusy program/erase active time by ry/by# 100 90 ns tghwl read recover time before write 0 0 ns tghel read recover time before write 0 0 ns twhwh1 program operation byte 11 11 us twhwh1 program operation word 11 11 us twhwh1 acc program operation (word/byte) 11 11 us twhwh2 sector erase operation 0.6 5 0.6 5 sec tbal sector add hold time 50 50 us trdp release from deep power down mode 200 200 us www.datasheet.in 49 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l ac characteristics- (2) symbol description 29gl128e (vcc=2.7v~3.6v) unit min. typ. max. taa valid data output after address 90 ns tpa page access time 25 ns tce valid data output after ce# low 90 ns toe valid data output after oe# low 25 ns tdf data output foating after oe# high 40 ns toh output hold time from the earliest rising edge of address,ce#, oe# 0 ns trc read period time 90 ns twc write period time 90 ns tcwc command write period time 90 ns tas address setup time 0 ns tah address hold time 45 ns tds data setup time 30 ns tdh data hold time 0 ns tvcs vcc setup time 500 us tcs chip enable setup time 0 ns tch chip enable hold time 0 ns toes output enable setup time 0 ns toeh output enable hold time read 0 ns toggle & data# polling 10 ns tws we# setup time 0 ns twh we# hold time 0 ns tcepw ce# pulse width 35 ns tcepwh ce# pulse width high 30 ns twp we# pulse width 35 ns twph we# pulse width high 30 ns tbusy program/erase active time by ry/by# 90 ns tghwl read recover time before write 0 ns tghel read recover time before write 0 ns twhwh1 program operation byte 11 us twhwh1 program operation word 11 us twhwh1 acc program operation (word/byte) 11 us twhwh2 sector erase operation 0.6 5 sec tbal sector add hold time 50 us trdp release from deep power down mode 200 us www.datasheet.in 50 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l figure 1. command write operation addresses ce# oe# we# din tds t ah data tdh tcs tch tcwc t wph t wp t oes t as vih vil vih vil vih vil vih vil vih vil v a v a: v alid address www.datasheet.in 51 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l read/reset operation figure 2. read timing waveforms addresses ce# oe# t aa we# vih vil vih vil vih vil vih vil v oh v ol high z high z d a t a v alid t oe t oeh tdf tce t rc outputs t oh add v alid www.datasheet.in 52 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l figure 3. reset# timing waveform t rh t rb1 t r p2 t r p1 t ready2 t ready1 r y/by# ce#, oe# reset# reset timing no t dur ing a utomatic algor ithms reset timing dur ing a utomatic algor ithms r y/by# ce#, oe# t rb2 we# reset# ac characteristics item description setup speed unit trp1 reset# pulse width (during automatic algorithms) min 10 us trp2 reset# pulse width (not during automatic algorithms) min 500 ns trh reset# high time before read min 200 ns trb1 ry/by# recovery time (to ce#, oe# go low) min 0 ns trb2 ry/by# recovery time (to we# go low) min 50 ns tready1 reset# pin low (during automatic algorithms) to read or write max 20 us tready2 reset# pin low (not during automatic algorithms) to read or write max 500 ns www.datasheet.in 53 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l erase/program operation figure 4. automatic chip erase timing waveform twc address oe# ce# 55h 2aah 555h 10h in progress complete va va ta s ta h tghwl tch twp tds tdh twhwh2 read status last 2 erase command cycle tbusy trb tcs twph we# data ry/by# www.datasheet.in 54 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l figure 5. automatic chip erase algorithm flowchart st ar t wr ite data aah address 555h wr ite data 55h address 2aah wr ite data aah address 555h wr ite data 80h address 555h yes no data=ffh ? wr ite data 10h address 555h wr ite data 55h address 2aah data# p olling algor ithm or t oggle bit algor ithm a uto chip er ase completed www.datasheet.in 55 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l figure 6. automatic sector erase timing waveform t wc address oe# ce# 55h 2aah sector address 1 sector address 0 30h in prog ress complete v a v a 30h sector address n t as t ah tbal tghwl tch t wp tds tdh t whwh2 read status last 2 er ase command cycle tb usy t rb tcs t wph we# data r y/by# 30h www.datasheet.in 56 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l figure 7. automatic sector erase algorithm flowchart st ar t wr ite data aah address 555h wr ite data 55h address 2aah wr ite data aah address 555h wr ite data 80h address 555h wr ite data 30h sector address wr ite data 55h address 2aah data# p olling algor ithm or t oggle bit algor ithm a uto sector er ase completed no last sector to er ase yes yes no data=ffh www.datasheet.in 57 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l figure 8. erase suspend/resume flowchart start write data b0h toggle bit checking q6 not toggled erase suspend yes no write data 30h continue erase reading or programming end read array or program another erase suspend ? no yes yes no erase resume www.datasheet.in 58 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l figure 9. automatic program timing waveforms figure 10. accelerated program timing diagram address oe# ce# a0h 555h p a pd status dout v a v a t as t ah tghwl tch t wp tds tdh t whwh1 last 2 read status cycle last 2 prog r am command cycle tb usy t rb tcs t wph we# data r y/by# wp#/a cc 250ns 250ns vhv (9.5v ~ 10.5v) vil or vih vil or vih www.datasheet.in 59 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l figure 11. ce# controlled write timing waveform address oe# ce# a0h 555h pa pd status dout va va ta s ta h tghwl tcepw tds tdh twhwh1 or twhwh2 tbusy tcepwh we# data ry/by# www.datasheet.in 60 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l figure 12. automatic programming algorithm flowchart st ar t wr ite data aah address 555h wr ite data 55h address 2aah wr ite prog r am data/address wr ite data a0h address 555h yes read again data: prog r am data? yes a uto prog r am completed data# p olling algor ithm or t oggle bit algor ithm ne xt address last w ord to be prog r amed no no www.datasheet.in 61 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l figure 13. silicon id read timing waveform ta a ta a ta a ta a tce to e to h to h to h to h tdf data out manufacturer id device id cycle 1 device id cycle 2 device id cycle 3 vhv vih vil add a9 add ce# a1 oe# we# add a0 data out data out data out data q0-q15 vcc 3v vih vil vih vil vih vil vih vil vih vil vih vil vih vil a2 disable enable www.datasheet.in 62 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l write operation status figure 14. data# polling timing waveforms (during automatic algorithms) tdf tce tch t oe t oeh t oh ce# oe# we# q7 q0-q6 r y/by# tb usy status data status data status data complement t r ue v alid data t aa t rc address v a v a high z high z v alid data t r ue www.datasheet.in 63 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l figure 15. data# polling algorithm notes: 1. for programming, valid address means program address. for erasing, valid address means erase sectors address. 2. q7 should be rechecked even q5="1" because q7 may change simultaneously with q5. read q7~q0 at v alid address (note 1) read q7~q0 at v alid address star t q7 = data# ? q5 = 1 ? q7 = data# ? (note 2) f ail p ass no no no y es y es y es www.datasheet.in 64 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l figure 16. toggle bit timing waveforms (during automatic algorithms) tdf tce tch t oe t oeh t aa t rc t oh address ce# oe# we# q6/q2 r y/by# tb usy v alid status (first read) v alid status (second read) (stops toggling) v alid data v a v a v a v a : v alid address v a v alid data www.datasheet.in 65 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l figure 17. toggle bit algorithm notes: 1. read toggle bit twice to determine whether or not it is toggling. 2. recheck toggle bit because it may stop toggling as q5 changes to "1". read q7-q0 t wice q5 = 1? read q7~q0 t wice pgm/ers f ail wr ite reset cmd pgm/ers complete q6 t oggle ? q6 t oggle ? no (note 1) yes no no yes yes star t www.datasheet.in 66 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l figure 18. byte# timing waveform for read operations (byte# switching from byte mode to word mode) ac characteristics word/byte configuration (byte#) parameter description test setup all speed options unit telf/telfh ce# to byte# from l/h max. 5 ns tfqz byte# from l to output hiz max. 30 ns tfhqv byte# from h to output active min. 90 ns figure 19. page read timing waveform tfhqv t elfh dout (q0-q7) dout (q0-q14) v a dout (q15) ce# oe# byte# q0~q14 q15/a-1 amax:a3 (a-1),a0,a1,a2 d a t a ce#/oe# note: ce#, oe# are enable. page size is 8 words in word mode, 16 bytes in byte mode. address are a2~a0 for word mode, a2~a-1 for byte mode. v alid add data 1 data 2 data 3 1'st add 2'nd add tpa taa 3'rd add tpa www.datasheet.in 67 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l figure 20. deep power down mode waveform ceb web add d a t a x x b 9 2aa 5 5 td p xx (don' t care) ab s ta n dby m ode a a 5 5 deep pow e r d o w n m ode trdp s ta n dby m ode item tpy max web high to release from deep power down mode trdp 100us 200us web high to deep power down mode tdp 10us 20us ac characteristics www.datasheet.in 68 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l figure 21. write buffer program flowchart wr ite cmd: data=aah, addr=555h wr ite cmd: data=55h, addr=2a a h wr ite cmd: data=25h, addr=sa sa: sector address of to be programme d page wr ite cmd: data=pwc, addr=sa pw c: progra m word count w r ite cmd: data=pgm_data, addr =pg m_addr p w c =0 ? wr ite cmd: data=29h, addr=sa polling sta t us yes p a s s n o n o write buffer abort w rite reset cmd to return to read mode p w c = p w c- 1 n o f a i l yes wa nt to abort ? yes n o n o yes return to re ad mode w r ite abort reset cmd to return to read mode w r ite a di ffe re nt sector a dd re ss t o ca use abort yes www.datasheet.in 69 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l recommended operating conditions at device power-up ac timing illustrated in figure a is recommended for the supply voltages and the control signals at device power- up. if the timing in the fgure is ignored, the device may not operate correctly. figure a. ac timing at device power-up vcc address ce# we# oe# data tvr taa tr or tf tr or tf tce tf vcc(min) gnd vih vil vih vil vih vil vih vil vih vil voh high z vol wp#/acc v alid ouput v alid address tvcs tr toe tf tr symbol parameter min. max. unit tvr vcc rise time 20 500000 us/v tr input signal rise time 20 us/v tf input signal fall time 20 us/v tvcs vcc setup time 500 us www.datasheet.in 70 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l latch-up characteristics erase and programming performance tsop pin capacitance notes: 1. typical program and erase times assume the following conditions: 25c, 3.0v vcc. programming specifca - tions assume checkboard data pattern. 2. maximum values are measured at vcc = 3.0 v, worst case temperature. maximum values are valid up to and including 100,000 program/erase cycles. 3. erase/program cycles comply with jedec jesd-47e & a117a standard. 4. exclude 00h program before erase operation. parameter symbol parameter description test set typ max unit cin2 control pin capacitance vin=0 7.5 9 pf cout output capacitance vout=0 8.5 12 pf cin input capacitance vin=0 6 7.5 pf min. max. input voltage voltage difference with gnd on wp#/acc and a9 pins -1.0v 10.5v input voltage voltage difference with gnd on all normal pins input -1.0v 1.5vcc vcc current -100ma +100ma all pins included except vcc. test conditions: vcc = 3.0v, one pin per testing parameter limits units min. typ. (1) max. (2) chip erase time 256mb 128 300 sec 128mb 64 150 sec sector erase time 0.6 5 sec chip programming time 256mb 100 350 sec 128mb 50 180 sec word program time 11 360 us total write buffer time 200 us acc total write buffer time 100 us erase/program cycles 100,000 cycles www.datasheet.in 71 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l ordering information part no. access time (ns) package remark mx29gl256ehmc-90q (note 2) 90 70 pin ssop pb-free (note 1) mx29gl256ehxfi-90q 90 64 lfbga pb-free (note 1) mx29gl256elxfi-90q 90 64 lfbga pb-free (note 1) mx29gl256ehxci-90q 90 64 fbga pb-free (note 1) mx29gl256elxci-90q 90 64 fbga pb-free (note 1) mx29gl256eht2i-90q 90 56 pin tsop pb-free (note 1) mx29gl256elt2i-90q 90 56 pin tsop pb-free (note 1) note : 1. 90q covers 2.7v~3.6v for 100ns and 3.0v~3.6v for 90ns. 2. 70-pin ssop only for pachinko socket. mx29gl256e h/l part no. access time (ns) package remark MX29GL128Ehmc-90g (note 1) 90 70 pin ssop pb-free MX29GL128Ehxfi-90g 90 64 lfbga pb-free MX29GL128Elxfi-90g 90 64 lfbga pb-free MX29GL128Ehxci-90g 90 64 fbga pb-free MX29GL128Elxci-90g 90 64 fbga pb-free MX29GL128Eht2i-90g 90 56 pin tsop pb-free MX29GL128Elt2i-90g 90 56 pin tsop pb-free note : 1. 70-pin ssop only for pachinko socket. MX29GL128E h/l www.datasheet.in 72 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l part name description mx 29 gl 90 e h t2 i g option: g: lead-free with vcc: 2.7v~3.6v q: lead-free with restricted vcc: 3.0v~3.6v (note 1) speed: 90: 90ns tempera ture range: i: industrial (-40 c to 85 c) p a cka ge: boo t block type: h: highest address sector protected l: lowest address sector protected revision: e density & mode: 256: 256mb x8/x16 uniform block 128: 128mb x8/x16 uniform block gl: 3v page mode type: device: 29:flash 256 t2: 56-tsop m: 70ssop xf: lfbga (11mm x 13mm) xc: fbga (10mm x 13mm) note 1: 90q covers 2.7v~3.6v for 100ns and 3.0v~3.6v for 90ns www.datasheet.in 73 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l package information www.datasheet.in 74 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l www.datasheet.in 75 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l www.datasheet.in 76 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l www.datasheet.in 77 p/n:pm1435 rev. 0.03, mar. 06, 2009 mx29gl256e h/l MX29GL128E h/l revision history revision no. description page date 0.01 1. to added 128mb information all feb/18/2009 2. to added "advance sector protection" information p31~p36 3. removed "sector group protect/unprotectd" information 0.02 1. modifed dc characteristics (isb, idpd) p45 feb/26/2009 2. modifed the program resume to next suspend waiting time from p28 400us to 5us 3. added the vcc range description of 29gl256e p1,47,70,71 4. modifed the chip erase time from 100s/256mb, 50s/128mb to p69 128s/256mb, 64s/128mb 5. revised ac characteristics: data output foating after oe# high p47 6. modifed copyright description p76 7. modifed array architecture description p5 8. modifed command operations description p28 9. modifed lock register bits table p32 0.03 1. change title from "advanced information" to "preliminary" p2 mar/06/2009 2. added 64-csp dimensions "11x13x1.4mm, p:1.0mm, b:0.55mm" p2,3,71, p72,76 3. modifed content error www.datasheet.in 78 m acronix i nternational c o., l td. macronix offces : taiwan headquarters, fab2 macronix, international co., ltd. 16, li-hsin road, science park, hsinchu, taiwan, r.o.c. tel: +886-3-5786688 fax: +886-3-5632888 taipei offce macronix, international co., ltd. 19f, 4, min-chuan e. road, sec. 3, taipei, taiwan, r.o.c. tel: +886-2-2509-3300 fax: +886-2-2509-2200 macronix offces : china macronix (hong kong) co., limited. 702-703, 7/f, building 9, hong kong science park, 5 science park west avenue, sha tin, n.t. tel: +86-852-2607-4289 fax: +86-852-2607-4229 macronix (hong kong) co., limited, suzhou offce no.5, xinghai rd, suzhou industrial park, suzhou china 215021 tel: +86-512-62580888 ext: 3300 fax: +86-512-62586799 macronix (hong kong) co., limited, shenzhen offce room 1401 & 1404, blcok a, tianan hi-tech plaza tower, che gong miao, futiandistrict, shenzhen prc 518040 tel: +86-755-83433579 fax: +86-755-83438078 http : //www.macronix.com macronix international co., ltd. reserves the right to change product and specifcations without notice. macronix offces : japan macronix asia limited. nkf bldg. 5f, 1-2 higashida-cho, kawasaki-ku kawasaki-shi, kanagawa pref. 210-0005, japan tel: +81-44-246-9100 fax: +81-44-246-9105 macronix offces : korea macronix asia limited. #906, 9f, kangnam bldg., 1321-4, seocho-dong, seocho-ku, 135-070, seoul, korea tel: +82-02-588-6887 fax: +82-02-588-6828 macronix offces : singapore macronix pte. ltd. 1 marine parade central, #11-03 parkway centre, singapore 449408 tel: +65-6346-5505 fax: +65-6348-8096 macronix offces : europe macronix europe n.v. koningin astridlaan 59, bus 1 1780 wemmel belgium tel: +32-2-456-8020 fax: +32-2-456-8021 macronix offces : usa macronix america, inc. 680 north mccarthy blvd. milpitas, ca 95035, u.s.a. tel: +1-408-262-8887 fax: +1-408-262-8810 mx29gl256e h/l MX29GL128E h/l macronix's products are not designed, manufactured, or intended for use for any high risk applications in which the failure of a single component could cause death, personal injury, severe physical damage, or other substan - tial harm to persons or property, such as life-support systems, high temperature automotive, medical, aircraft and military application. macronix and its suppliers will not be liable to you and/or any third party for any claims, injuries or damages that may be incurred due to use of macronix's products in the prohibited applications. copyright? macronix international co. ltd. 2008. all rights reserved. macronix, mxic, mxic logo, mx logo, are trademarks or registered trademarks of macronix international co., ltd.. the names and brands of other companies are for identifcation purposes only and may be claimed as the property of the respective companies. www.datasheet.in |
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